A novel technique for a self-equalized DISTRIBUTED AMPLIFIER is presented by showing the analogy between transversal filters and DISTRIBUTED AMPLIFIER topologies. The appropriate delay and gain coefficients of AMPLIFIER circuit are obtained by a Fourier expansion of the raised cosine spectrum in the frequency range of 0-40GHz.

In this paper a new method for the design of a linear phase DISTRIBUTED AMPLIFIER in 180nm CMOS technology is presented. The method is based on analogy between transversal filters and DISTRIBUTED AMPLIFIERs topologies. In the proposed method the linearity of the phase at frequency range of 0-50 GHz is obtained by using proper weighting factors for each gain stage in cascaded AMPLIFIER topology. These weighting factors have been extracted using MATLAB software. Finally, by plotting the frequency response of the AMPLIFIER resulted from MATLAB code and also simulation from ADS, the phase linearity of the designed AMPLIFIER is shown.

In this paper, a DISTRIBUTED AMPLIFIER (DA) by using HEMT technology for ultra-wideband application is presented.Creation of DISTRIBUTED integrated circuit has been investigated for approximately seventy years rapidly to developing semiconductor process technologies in the modern IC design. By using of this method, multiple parallel signals are combined and obtain to increase the bandwidth, enhanced power combining amplitude, and novel design capabilities for IC process. The circuit was designed and simulated in ED02AH technology by using ADS2010. The 4-stage design achieves 15.5 dB of power gain (± 0.5 dB) from 3.1 to 10.6 GHz. Reflected power of the input and output from loads matched to 50 Ohm are all below -10 dB over the bandwidth of the device, as is power transmitted from the output to the input. The device is stable for a wide range of input and output loads.

In this paper, a low power 2×3 matrix DISTRIBUTED AMPLIFIER (DA) with tapper transmission lines is introduced in 180 nm CMOS technology. The matrix structure is used to provide the mechanisms of multiplication and additive of the current for increasing the gain and reducing the power consumption. In the input stage, a controllable cascade gain cell is used to expand the bandwidth and remove to need the additional capacitors in the input gate and central transmission lines. Moreover, the terminating resistor of the input gate transmission line is replaced with an RL network. The proposed DISTRIBUTED AMPLIFIER is designed and simulated using TSMC 0.18 µm CMOS technology in Cadence Spectre-RF over the frequency of 1-30 GHz. Operated at 1 V, the proposed DA consumes 25.16 mW. Simulation results show that the proposed DA achieves a direct power gain (S21) of 12±1 dB with an average NF of 5.75 dB and average IIP3 of -6.11 over the 1–24 GHz band of interest. The input and output return losses are also more than 10 dB.

In this paper, a new structure composed of a negative capacitance and resistance is presented in order to increase gain and bandwidth of DISTRIBUTED AMPLIFIERs. The proposed structure is used at the gate transmission line of the DISTRIBUTED AMPLIFIER and the obtained circuit has been simulated using 0.13mm CMOS model. The negative capacitance at the gate transmission line decreases parasitic effects of gain cells and increases AMPLIFIER bandwidth and accordingly increases voltage gain. The generated negative resistance decreases transmission lines losses and increases bandwidth. Simulated voltage gain is 15dB with ±0.5odB gain flatness over 0.5-49 GHz frequency band. Circuit input and output are matched with 50Ω resistance; and input and output return losses are -8.15 dB and -9.2 dB, respectively. This circuit has a noise figure less than 4.6 and its power consumption is 99 mW from 1.8 V power supply.

Pseudo-differential DISTRIBUTED AMPLIFIER (PDDA) is an effective method in increasing the bandwidth of a broadband AMPLIFIER. This study investigates different methods with same power consumption and chip area for enhancement gain-bandwidth in a cascaded pseudo differential DISTRIBUTED AMPLIFIER (CPDDA) and compare them. The choice of optimal design depends on the gmRo parameter of the PDA cells. The proposed circuits have been implemented in 0. 18-μ m RF-CMOS technology. The simulation results show that in this technology, in order to obtain a 0-40GHz bandwidth that requires low gmof the PDA's cell-transistor, two cascaded PDDA with three stages has a better performance than a three cascaded PDDA with two stages. In two cascaded PDDA with three stages structure, a gain of 10dB can be achieved in the bandwidth of 40GHz in 0. 18-μ m RF-CMOS technology. In this AMPLIFIER, parameters S11, S22, S12, are-12,-10, and-16 dB, respectively and noise figure is equal to 4. 6 and P1dB is +3. 5dBm. This AMPLIFIER has 230mW power consumption and a chip area of 0. 63 mm2. These values show the good performance of the proposed AMPLIFIER, compared to the results of previous works on similar AMPLIFIERs.

In this paper, we analyze a DISTRIBUTED AMPLIFIER based on input/output attenuation compensation. The analysis is carried out for a HEMT transistor; and a constant-k section filter is used to calculate the AMPLIFIER’s characteristics such as attenuation factor, phase constant and gain. The proposed design approach enables us to examine the tradeoff among the variables, which include the type and the number of devices, and the impedance and cutoff frequency of the lines. Consequently, we arrive at a design which gives the desired frequency response with significant bandwidth enhancement of around 70% with about 10% increase in circuit size. The simulation carried out by Advance Design System (ADS) software. Excellent agreement is shown when the theoretically predicted response of a typical AMPLIFIER is compared with the result of the computer-aided analysis (simulation).

In this paper two dimensional wave propagation is used for power combining in drain nodes of a DISTRIBUTED AMPLIFIER (DA). The proposed two dimensional DA uses an electrical funnel to add the currents of drain nodes. The proposed structure is modified due to gate lines considerations. Total gain improvement is achieved by engineering the characteristic impedance of gate lines and also make appropriate variation in the output of gain cells. All variations are done with respect to input and output reflection loss considerations. Analytical expression for the gain of the proposed DA is presented and design considerations for electrical funnel are discussed. Based on two dimensional power combining a wide band DA is simulated using TSMC 0. 18 CMOS model in ADS which consumes 49. 42 mw from 1. 2V power supply. Good agreement between the proposed DA gain and calculated value is achieved. Although one stage DA is used, the final results yield a high figure of merit (FOM) in 0. 18 CMOS technology. The final design shows 11. 1 dB gain from near DC to 23. 6 GHz, noise figure between 3 to 5. 2dB and maximum output power of 7. 1dBm at 1-dB output compression point (OP1dB).

In this paper, analysis, simulation and design of a DISTRIBUTED AMPLIFIER (DA) with 0.13mm CMOS technology in the frequency range of 3-40 GHz is presented. Gain cell is a current reused circuit which is optimum in gain, noise figure, bandwidth and also power dissipation. To improve the noise performance in the frequency range of interest, a T-matching low pass filter LC network is utilized at the input gate of the designed AMPLIFIER. By this means, the proposed cascaded DA shows about 28% improvements in noise figure and 20% improvement in the gain compared with those of the other well-known configuration. To show the capability of the proposed method we also compared the figure of merit of the proposed AMPLIFIER with those obtained with the other researches and showed that this figure is around 38% higher than that of those achieved by other researchers. The figure of merit includes gain, bandwidth, power consumption and also noise figure.

Background and Objectives: In this paper, a new design strategy was proposed in order to enhance bandwidth and efficiency of power AMPLIFIER. Methods: To realize the introduced design strategy, a power AMPLIFIER was designed using TSMC CMOS 0. 18um technology for operating in the Ka band, i. e. the frequency range of 26. 5-40GHz. To design the power AMPLIFIER, first a power divider (PD) with a very wide bandwidth, i. e. 1-40GHz, was designed to cover the whole Ka band. The designed Doherty power AMPLIFIER consisted of two different amplification paths called main and auxiliary. To amplify the signal in each of the two pathways, a cascade DISTRIBUTED power AMPLIFIER was used. The main reason for combining the DISTRIBUTED structure and cascade structure was to increase the gain and linearity of the power AMPLIFIER. Results: Measurements results for designed power divider are in good agreement with simulations results. The simulation results for the introduced structure of power AMPLIFIER indicated that the gain of proposed power AMPLIFIER at the frequency of 26-35GHz was more than 30dB. The diagram of return loss at the input and output of power AMPLIFIER in the whole Ka band was less than-8dB. The maximum Power Added Efficiency (PAE) of the designed power AMPLIFIER was 80%. The output P1dB of the introduced structure was 36dB, and the output power of power AMPLIFIER was 36dBm. Finally, the IP3 value of power AMPLIFIER was about 17dB. Conclusion: The strategy presented in this paper is based on usage of Doherty and DISTRIBUTED structures and a new wideband power divider to benefit from their advantages simultaneously.